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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : xaw2vhdl
--  /   /         Filename : SubAdder2x24.vhd
-- /___/   /\     Timestamp : 12/08/2009 14:29:53
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-st I:\\My_designs\Now\Sirius\VHDL\xilinxcoregen\.\SubAdder2x24.xaw I:\\My_designs\Now\Sirius\VHDL\xilinxcoregen\.\SubAdder2x24
--Design Name: SubAdder2x24
--Device: xc5vlx110-1ff676
--
-- Module SubAdder2x24
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity SubAdder2x24 is
    generic(
        ACASCREG	: integer		:= 1;
        ALUMODEREG	: integer		:= 1;
        AREG		: integer		:= 1;
        AUTORESET_PATTERN_DETECT		: boolean		:= FALSE;
        AUTORESET_PATTERN_DETECT_OPTINV		: string		:= "MATCH";
        A_INPUT		: string		:= "DIRECT";
        BCASCREG	: integer		:= 1;
        BREG		: integer		:= 1;
        B_INPUT		: string		:= "DIRECT";
        CARRYINREG	: integer		:= 1;
        CARRYINSELREG	: integer		:= 1;
        CREG		: integer		:= 1;
        MASK            : bit_vector            := X"3FFFFFFFFFFF";
        MREG		: integer		:= 1;
        MULTCARRYINREG	: integer		:= 1;
        OPMODEREG	: integer		:= 1;
        PATTERN         : bit_vector            := X"000000000000";
        PREG		: integer		:= 1;
        SEL_MASK	: string		:= "MASK";
        SEL_PATTERN	: string		:= "PATTERN";
        SEL_ROUNDING_MASK	: string	:= "SEL_MASK";
        USE_MULT	: string		:= "NONE";
        USE_PATTERN_DETECT	: string	:= "NO_PATDET";
        USE_SIMD	: string		:= "TWO24"
        );
    port ( AB_IN      : in    std_logic_vector (23 downto 0); 
        C_IN       : in    std_logic_vector (23 downto 0); 
        D_IN       : in    std_logic_vector (23 downto 0); 
        F_IN       : in    std_logic_vector (23 downto 0); 
        ALUMODE_IN : in    std_logic_vector (3 downto 0); 
        CE_IN      : in    std_logic; 
        CLK_IN     : in    std_logic; 
        RST_IN     : in    std_logic; 
        P_OUT      : out   std_logic_vector (23 downto 0);
        Q_OUT      : out   std_logic_vector (23 downto 0));
end SubAdder2x24;

architecture BEHAVIORAL of SubAdder2x24 is
    signal GND_BUS_3  : std_logic_vector (2 downto 0);
    signal GND_BUS_18 : std_logic_vector (17 downto 0);
    signal GND_BUS_30 : std_logic_vector (29 downto 0);
    signal GND_BUS_48 : std_logic_vector (47 downto 0);
    signal GND_OPMODE : std_logic;
    signal P_float    : std_logic_vector (15 downto 0);
    signal VCC_OPMODE : std_logic;
begin
    GND_BUS_3(2 downto 0) <= "000";
    GND_BUS_18(17 downto 0) <= "000000000000000000";
    GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
    GND_BUS_48(47 downto 0) <= 
    "000000000000000000000000000000000000000000000000";
    GND_OPMODE <= '0';
    VCC_OPMODE <= '1';
    DSP48E_INST : DSP48E
    generic map( ACASCREG => ACASCREG,
        ALUMODEREG => ALUMODEREG ,
        AREG => AREG ,
        AUTORESET_PATTERN_DETECT => AUTORESET_PATTERN_DETECT ,
        AUTORESET_PATTERN_DETECT_OPTINV => AUTORESET_PATTERN_DETECT_OPTINV ,
        A_INPUT => A_INPUT ,
        BCASCREG => BCASCREG ,
        BREG => BREG ,
        B_INPUT => B_INPUT ,
        CARRYINREG => CARRYINREG ,
        CARRYINSELREG => CARRYINSELREG ,
        CREG => CREG ,
        MASK => MASK ,
        MREG => MREG ,
        MULTCARRYINREG => MULTCARRYINREG ,
        OPMODEREG => OPMODEREG ,
        PATTERN => PATTERN ,
        PREG => PREG ,
        SEL_MASK => SEL_MASK ,
        SEL_PATTERN => SEL_PATTERN ,
        SEL_ROUNDING_MASK => SEL_ROUNDING_MASK ,
        USE_MULT => USE_MULT ,
        USE_PATTERN_DETECT => USE_PATTERN_DETECT ,
        USE_SIMD => USE_SIMD )
    port map (
        A(29 downto 6)=>D_IN(23 downto 0),
        A(5 downto 0)=>AB_IN(23 downto 18),
        ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
        ALUMODE(3 downto 0)=>ALUMODE_IN(3 downto 0),
        B(17 downto 0)=>AB_IN(17 downto 0),
        BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
        C(47 downto 24)=>F_IN(23 downto 0),
        C(23 downto 0)=>C_IN(23 downto 0),
        CARRYCASCIN=>GND_OPMODE,
        CARRYIN=>GND_OPMODE,
        CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
        CEALUMODE=>CE_IN,
        CEA1=>CE_IN,
        CEA2=>CE_IN,
        CEB1=>CE_IN,
        CEB2=>CE_IN,
        CEC=>CE_IN,
        CECARRYIN=>CE_IN,
        CECTRL=>CE_IN,
        CEM=>CE_IN,
        CEMULTCARRYIN=>CE_IN,
        CEP=>CE_IN,
        CLK=>CLK_IN,
        MULTSIGNIN=>GND_OPMODE,
        OPMODE(6)=>GND_OPMODE,
        OPMODE(5)=>VCC_OPMODE,
        OPMODE(4)=>VCC_OPMODE,
        OPMODE(3)=>GND_OPMODE,
        OPMODE(2)=>GND_OPMODE,
        OPMODE(1)=>VCC_OPMODE,
        OPMODE(0)=>VCC_OPMODE,
        PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
        RSTA=>RST_IN,
        RSTALLCARRYIN=>RST_IN,
        RSTALUMODE=>RST_IN,
        RSTB=>RST_IN,
        RSTC=>RST_IN,
        RSTCTRL=>RST_IN,
        RSTM=>RST_IN,
        RSTP=>RST_IN,
        ACOUT=>open,
        BCOUT=>open,
        CARRYCASCOUT=>open,
        CARRYOUT=>open,
        MULTSIGNOUT=>open,
        OVERFLOW=>open,
        P(47 downto 24)=>Q_OUT(23 downto 0),
        P(23 downto 0)=>P_OUT(23 downto 0),
        PATTERNBDETECT=>open,
        PATTERNDETECT=>open,
        PCOUT=>open,
        UNDERFLOW=>open);
    
end BEHAVIORAL;


